گیرنده پهنای باند

Wideband Receiver

A 133MHz Differential Amplifier with External Gain Set, Impedance Matching to a 75Ω Source and Level Shifting

Complete single ended 75Ω input impedance to differential out, level shifting 2.5V input to 1.25V differential common mode, single ended to differential gain of 2 using external resistors circuit example

به دست آوردن امپدانس برای یک تقویت کننده دیفرانسیل با مقاومت ثابت

Single ended to 50Ω Input Diff amp Example with Equations. By AC coupling Impedance matching is the only issue. AC coupling also realizes Auto input to output common mode level shifting

Debugging the LTC6946: Getting the PLL to Lock

The DC1705 and the PLLWizard software provide a complete evaluation system for the LTC6946 that makes it easy to determine how the part will behave in your system. However, a common problem can occur when designing any PLL system - what if the PLL is not locking to the proper frequency?  In cases where the LTC6946 RF output is alive but is toggling at the wrong frequency, the DC1705 and Linear Technology's PLLWizard software can help get your design back on track

After extensive debugging and discounting of many hardware issues that might prevent the PLL from locking, returning to the DC1705 can provide insight into your design. Click on “Read All” in PLLWizard after the red LED on the demoboard lights up to indicate that the PLL is locked. This reads back the register values written to the LTC6946. Go to the “Registers” tab in PLLWizard and compare the register values there to those read back from the LTC6946 in your system

Confirm that all the bit values read back from the LTC6946 in your system match those you read back from the demoboard while using a similar reference clock frequency. If the registers in both your system and in the demoboard match, but the part still refuses to lock to the correct frequency, the problem may be with a single register bit

The LTC6946 uses multiple internal VCO sub-bands to cover its entire output frequency range. Every time the LTC6946 is powered up or its frequency is changed (through a change in either one of these or a combination of them: N-Divider, R-Divider, or the reference clock rate), the IC runs an internal search algorithm to find the correct VCO sub-band to use. The user does not have to worry about this process except for letting the IC know that the VCO frequency is to be changed. This can be done by writing a “1” to the “CAL” bit in register h07. This bit will reset itself following the initiation of the calibration cycle. This explains why when you look at this particular register value read back by PLLWizard you find it to be “0” and not “1”. So make sure that when you program the LTC6946 for the first time or when you change its VCO frequency, this bit is set to “HIGH”

حداکثر SNR، انتظار: کاهش لرزش ساعت

When designing the clock network for a high speed ADC one of the most critical parameters is jitter.  The amount of clock jitter will set the maximum SNR that you can achieve for a given input frequency.  Most modern high speed ADCs have about 80fs of jitter, and the encode clock of the ADC should be in that ball park.  It certainly should be less that 1ps for maximum performance of the ADC.

The relationship between SNR and jitter is given by this equation

Where fin is the frequency of the input signal, and tj is the jitter of the clock.  The equation shows that for a high frequency input signal and a fixed amount of jitter the maximum SNR will decrease.  This is because a faster slewing signal will have more of a voltage error with a given amount of jitter

For input signals that have relatively low frequency content, under 1MHz lets say, the clock jitter becomes less

critical, but when the frequency of the input signal is several hundred megahertz the jitter on the clock will be the

dominate source of error, and will be the limiting factor for SNR

Here is an easy chart that shows how SNR degrades with input frequency and jitter from the clock

Simply find the input frequency you are using on the X axis, and the required SNR on the Y axis, and you can see exactly how little jitter you will need on your clock to achieve the desired SNR.  In order to combine the jitter from the clock with the jitter from the ADC you will need to sum the two terms in terms of power

For example if you have a 100MHz input signal, and you want 78dB of SNR you will need a clock source with less than 200fs of jitter.  Typical FPGAs will have up to 50ps of additive jitter, and should not be used an ADC clock.  Typically VCXOs and low jitter PLLs are the best ADC clock sources

It is important to note that these equations are derived from standard sampling theory and apply to all ADCs, from any manufacturer

When designing a system with a high speed ADC it is important to consider clock jitter.  It can severely limit the SNR you can achieve in a system, and can potentially be a show stopped in a system design.  Keeping the clock jitter as low as possible is just as important as the design of the front end circuitry.  It should not be an afterthought, but should be considered in the first stages of the design